The present invention relates to a wiring technique to be implemented in a semiconductor integrated circuit having a plurality of wiring layers, and more particularly to a multilayer wiring method of wiring those signal wires having high modification-requisite possibility among signal wires permitted to modify using an upper wiring layer or layers in a semiconductor integrated circuit chip (LSI) for the purpose of facilitating change of wires for modification or repair of the LSI therein.
The logical circuit mounted on a semiconductor integrated circuit chip used for arranging a logical unit such as a computer circuit has often required change of logic arrangement under development of the logical circuit. The change of the logical arrangement mounted on an LSI chip is carried out by changing wiring patterns of aluminium wires between logical gates wired in two or more layers in a manner to cover the top of the LSI chip.
This type of change of logical arrangement has often required a slight change such as change of part of a signal wire only. Just for the change of wiring patterns, however, it takes too much time to remanufacture an LSI chip. For modification a of portion of a signal wire, therefore, a technique has been developed of disconnecting unnecessary wires by applying a laser or a focused ion beam on the top of the manufactured LSI chip and connecting signal wires of a wiring layer mounted on the LSI chip by means of laser chemical vapor deposition (referred to as CVD) or a focused ion beam CVD method (see JP-A-62-229956).
Further, as described in JP-A-62-298134, for the purpose of facilitating modification or repair of wiring on an LSI chip, there has been proposed a technique of providing a spare wire between the logical gates and modifying or repairing the wiring connection by using the spare wire. This technique is designed so that a conductive layer is provided on the same layer level as the upper-layer spare wire on a lower-layer spare wire near a crossing portion between a lower-layer spare wire and an upper-layer spare wire and the conductive layer is connected to the lower-layer spare wire. This design results in making it possible to form a more shallow connecting hole for modifying connection between the lower-layer spare wire and the upper-layer spare wire, thereby improving reliability about the modification.
The foregoing prior art, however, is required to pull up parts of all the wiring patterns to an upper layer for enhancing the reliability about modified or repaired wiring of an LSI chip. Since the LSI chip normally provides cell terminals in the bottom layer of the wiring layers, it is necessary to pull up the wiring patterns through through-holes at one time or in a one-layer-by-one-layer manner from the bottom layer.
In case of employing the method of leading the wiring patterns out through the through-holes, it is quite difficult for the current manufacturing process of the semiconductor integrated circuit to create the through-hole in the chip, in particular, more difficult if more wiring layers such as four layers are formed, often resulting in the lowering of reliability and a yield of the semiconductor integrated circuit. In general, therefore, another method has been employed of leading signal wires out to the top layer in a one-layer-by-one-layer manner from a bottom layer.
The main cause of increasing the wiring layers of an LSI chip in number is to secure the wiring channels against the logical gates packed on a small area. However, if parts of all the wiring patterns are led out to the top layer as stated above, it is substantially the same as taking a roundabout way and thus consumes the wiring channels wastefully. It results in disadvantageously bringing about an unwired state of necessary wires.
The modification of the LSI does not require all the signal wires to be modified. In principle, clock-system wires such as clock supply signal lines are not required to be modified, because the modification of the clock-system wires brings about the change of timing about signal delays between the logical gates and will not provide sufficient performance. Of the signal wires, there exist such signal wires which do not need to be modified.